Fabrication of 100nm Nano Pillars on Silicon

Document Type : Research Paper

Authors

1 Electronics &Telecommunication Engineering, Symbiosis Institute of Technology, Symbiosis International University, Pune.

2 Department of Electronics & Telecommunication Engineering, Symbiosis Institute of technology, Symbiosis International University, Pune..

10.22052/jns.2021.240440.2197

Abstract

The main objective of the project was to fabricate a vertical Gate All Around (GAA) p-i-n doped Tunneling Field Effect Transistor (TFET) device for which attaining precise nanopillar structure were needed, to be optimized and achieved. This paper specifically focused on fabrication of Nano pillar on Silicon wafer using Hydrogen Silsesquioxane (HSQ). Initially we experimented with two methods Plasma Asher and AMAT Etch chamber. We have chosen HSQ resist for patterning high-resolution 100 nm circular dot structures for the fabrication of densely packed suspended vertical Si Nano pillars. This provides high etching resistivity of HSQ and better convenience of pattern transfer and selectivity from resist to various materials. IN addition, epitaxial semiconductor Si wafers with different semiconductor layers have been directly implemented to render nanopillars with self-aligned and well-defined homo or hetero junction properties. These structures may be used to analyze evidence of the primary design of devices such as vertical surround Gate field effect transistors.

Keywords


INTRODUCTION
The continuous CMOS device scaling is suffering from short channel effects, increased Off-state leakage current and non-scalability of the operating supply voltage (Vdd). All these factors are compelling for different geometry transistors. GATE-ALL AROUND (GAA) or wrap around gate nanowire Compared to other gate designs such as double or tri-gated transistors, Field Effect Transistors (FET) have attracted a lot of attention for better electrostatic control [1]– [5]. To build up a cognitive computing system that will closely emulate biological neuron structure, present CMOS transistor should be modelled as low energy switching devices with high scalability. Therefore, we propose to fabricate a vertical wrap around nano-wire p-type Tunnel FET on the Si substrate. To fabricate such an ultrashort channel vertical nano-wire TFET devices of minimum footprint, without suffering thermal budget limit and serious short-channel effect (SCEs), was the main goal of the proposed structure. In addition, epitaxial grown semiconductor Si wafers with various semiconductor layers can be implemented directly to make nanopillar with homo or hetero junction properties that are self-aligned and well-defined. Such structures may be used to examine evidence of the principal architecture of devices such as the transistors for vertical surround Gate field effect [6]. EBL is difficult to apply to the fabrication of the silicon nanopillar array with large area [7].  Basically, the proposed vertical GAA nanowire p-TFET would include dominant fabrication stages like one of the prominent stages is Silicon nanowire array fabrication by applying Proximity effect correction (PEC), thereby Electron beam lithography and finally Reactive ion etching (RIE) using Hydrogen Silsesquioxane (HSQ) hard mask. This paper presents optimization recipe for Electron beam lithography (EBL) patterning of 100nm dots on HSQ resist. 
The class of inorganic compounds with the chemical formula [HSiO3/2] * n is Hydrogen Silsesquioxane (HSQ). HSQ is an e-beam resistant negative-acting material that works well. It’s not a normal resist, because it’s not an organic polymer, it’s a spin-on-glass material that after production actually leaves behind a SiO2 material in exposed are as It is often referred to by the old trade name FOX (which was short for Flowable Oxide). It is marketed by DOW CORNING as XR-1541 now. A significant role in the achievable resolution has been stated to be the thickness of the coated resist. It is immune to very high resolution, but needs a high dose, and so exposure is slower with Silsesquioxane with hydrogen (R = H). For the patterning and generation of semiconductor nanostructures, a low-cost Nano sphere lithography approach offers a possible alternative to traditional top-down manufacturing techniques [8]. The initial nanoparticle mask can regulate the shape and density of the nanopillar, which can be controlled by adjusting the initial film thickness and temperature of the annealing process. The silica nanopillar displays lower reflectance due to the moth-eye effect [9]. In a number of fields such as photonics and nano photonics [10-11], vertical nanostructures having aspect ratios greater than 1 are important.
Y. Guerfi et al., demonstrated with the top-down manufacturing of ultra-high density vertical silicon nanowire networks, 100 percent yield, and precise control of both diameter and position. First, e-beam lithography has been modelled dense and well-defined Nano pillar networks using a negative tone e-beam resistant Hydrogen Sylses Quioxane (HSQ) [12].  Though there are lots many techniques suggested and implemented we opt novelty in optimizing fabrication techniques for implementing Nanopillar which provides good selectivity for patterning material and improving the process of etching to remove HSQ after post processing.  In our experiment, we have chosen top - down approach with HSQ resist for patterning high-resolution 100 nm circular dot structures for the fabrication of densely packed suspended vertical Si nano pillars due to the high etch resistance of HSQ and the selectivity freedom of transfer of pattern from resist to various material.

MATERIALS AND METHODS
Critical issues that occur during the manufacture by e-beam lithography of high-density nanostructures were considered by Jung‐Sub Wi et al. They made a 25-nm-pitch Si nanopillar array and a 15-nm-pitch nanodot resist array [13]. In combination with e-beam lithography, etching of the HSQ resist residues shows excellent flexibility, anisotropy, and selectivity of the process [14]. A circular dot pattern of Feature size 100nm successfully written by us on Materials like silicon, silicon nitride and silicon dioxide using HSQ negative resist by optimizing EBL parameters to 20kV (Electric High Tension) EHT, 7.5 µm aperture within dose factor window of 360 µC to 520 µC. Silicon oxide (SiOx) had also shown excellent efficiency of resistance switching [15]. The best results were found for plain Silicon sample.
We have used DOW Corning’s XR-1541-006 E Beam resist in MIBK, a 6% dilution, for our experiment. The details of steps executed for experiment is listed below:
For Si wafer cleaning sample was dipped in acetone and then in isopropyl alcohol (IPA) for few second sample was dried using low pressure nitrogen gun.
Cleaned Si sample was baked on hotplate for 15 min at 170 C for dehydration. Sample was being spin coated with 6% HSQ using 4000 rpm and 2000 rpm for 45 minutes after which was kept at 250 Celsius for 2 minutes.
iii)       Patterning of 30x30 µm solid squares with an array of 25 x 25 of 100nm circular dots   
                  with a pitch of 300 nm as shown in following Fig. 1.
vi)      Finally, sample was exposed to 20Kv Electric High Tension (EHT) with 60 µm Aperture  
for solid squares and 7.5µm Aperture for circular dots. Developed in 25% TMAH cold    
solution for 1-5 seconds and rinse in flowing distilled water for 30 sec. Developed 
sample was sent to take scanning electron microscope (SEM) Images.
Above process was successfully implemented for Silicon Nitride and Silicon Dioxide Sample. In case of both, the dose factor window for HSQ found out to be 320 µC- 520 µC. After the lift-off phase, gold (Au) Nano meshes with customizable nanostructures were achieved. Because of the aperiodic structures of disordered apertures, Au Nanomesh exhibited strong optoelectronic properties and non-iridescence without angle dependence [16]. Patterns below 320 µC dose were not coming good. Hence Nano pillars were developed with Plain Silicon wafer. Following Fig. 2 shows process flow for development of nano pillars on Si wafer
Following Fig. 3 shows results of a circular dot pattern of feature size 100nm and concluded that it can be successfully written on materials like silicon, using HSQ negative resist by optimizing EBL parameters to 20kV EHT, 7.5 µm aperture within dose factor window of 360 µC to 520 µC.

Optimization recipe for 100nm Silicon pillar etching
The control of the aspect ratio of the fabricated silicon nanostructures can be demonstrated by varying the RIE (reactive ion etching) power during the RIE process [17]. In our process of RIE, for reactive ion etching of silicon for making nano pillars with AMAT etch tool with RF Power of 800 W & Biased Power of 80 W, there were two chemistries available for Silicon Etching as shown in Fig. 4 below.    
                                             
AMAT etching using SF6 Chemistry
 We tried SF6 chemistry on AMAT etching tool using recipe keeping RF Power at 800 W, Biased Power at 80 W Pressure of 15mTorr, Gas used SF6 of 110sccm. Etch rate calculated earlier to15nm/sec with Time of 30 sec. As seen from fig. 5, this SF6 chemistry was too strong and powerful that patterned itself got white washed. But at the same time, we tried the CHF3 and CF4 chemistry and the results were somewhat encouraging. This is elaborated henceforth.

AMAT etching using CHF3 and CF4 Chemistry
The CHF3 and CF4 chemistry was tried on AMAT etching tool using following recipe. Taking lead from earlier AMAT experiment with SF6 chemistry, this time, the power was lowered to 500 W so as to protect the written pattern from getting damaged. The experiment was carried out with the recipe of keeping RF Power at 500-Watt, Biased Power of 50-Watt, Pressure of 15mTorr, Gas: CHF3 of 10sccm, CF4 of 100 sccm and Time set was for 20 sec. Fig. 6 & 7 shows the results of AMAT etched using CHF3 and CF4 chemistry (Si + HSQ) for 10 secs and 20 secs respectively.
The results obtained were found good compared to AMAT SF6 chemistry etching experiments. Some fallen pillar of 163 nm height was spotted in SEM. The surface was also less roughened. Atomic force microscopy (AFM) results confirmed the surface roughness.           
The results obtained with AMAT CHF3 and CH4 chemistry showed good signs that it can be more optimized for getting better results. So, the next strategy was to reduce the RF power as low as possible to get the controlled and faithful etching. Thus, next experiment was carried out with the following recipe.
RF Power of 400-Watt, Biased Power of 80-Watt, Pressure at 15mTorr, Gas used was CHF3 for 10sccm, CF4 for 100sccm, Total Time 30 secs for sample 1 & 60 secs for sample 2. These were the best results we obtained for etching. Fig. 8 shows the result of AMAT etched for 60 sec using CHF3 and CF4 chemistry (Si + HSQ).
Now the task was to measure the height of silicon pillar obtained and thereby, optimize the etching time. Fig. 9 shows the AFM surface image for Plasma etched for 2 min using CHF3 and O2 gases (SixNy + HSQ) whereas AFM profile measurement for Plasma etched for 2 min using CHF3 and O2 gases (SixNy + HSQ) is given in Fig. 10. AFM surface image for AMAT etched for 60 sec using CHF3 and CF4 chemistry (Si + HSQ) is shown in Fig. 11 specifying 3-D AFM image with amplitude information.

RESULTS AND DISCUSSION
The Table 1 below summarizes the result obtained from AMAT etching experiment. After Studying the results obtained, it came to notice that for 30 sec etching time, if the nano pillar height obtained is 170nm, then for 60 sec etching time, the nano pillar height obtained was 78 nm. This observation made it clear that HSQ’s masking effect is vanishing in between some range of 30 to 60 sec time. And thereafter, pillar etching is again started and so height of nano pillar is diminished at 60 sec time. Gold was vaporized on a flexible material, using electronic beam lithography to create the flexible electrode. Since Gold acts as flexible electrode [18]. Substrates made of gold-coated silicon dimer-nanopillar arrays have high sensitivity and reproducibility [19].
Thus, now task is of optimizing the etching time and improving the etching profile for getting the highest possible silicon pillar with HSQ resist of thickness 100nm as mask. So, eight Si+ HSQ samples were EBL patterned and etched with varying times as summarized below in Table 2.
The Field Emission Scanning Electron Microscopy (FESEM) results:
 Following Fig. 12 shows the FESEM image taken at tilt of 45˚ for AMAT etched using CHF3 and CF4 chemistry (Si + HSQ) with 30 sec etch time. The Field emission scanning electron microscopy (FESEM) images needed more tilt like 60˚ angle for getting better overview of the height of pillars. So, the FESEM imaging also needs to be done with more proficiency to have overall good results.
In the pursuit to increase aspect ratio of Si pillars, two more experiments were carried out like hardening of HSQ by thermal curing in oven by baking at 300C and the other one like Ultra Violet (UV) blanket exposure at higher doses like 1000mJ/cm2. But the effect observed was patterns were shrinking. Nanoimprint lithography (NIL) involves complex post processing design steps to obtained deep nanostructures [20]. As such fig. 13 manifests the reduction of diameter from 60 nm just after EBL to 40 nm after baking in oven and further to 20nm after etching showing SEM image after thermal curing of HSQ & after etching cured sample (Si + HSQ).
The tilt FESEM image for the above thermally cured and etched Si sample is shown in Fig. 14.

CONCLUSION
After so many optimization experiments carried out, it can be inferred that AMAT etching using CHF3 and CF4 chemistry worked out for better pattern transfer to form Silicon nano pillar.  After experimenting with different samples with different resist spinning & etching time, the results obtained was noted such that if the nano pillar height obtained is 170 nm for 30 seconds etching time; then for 60 seconds etching time, the height of the nano pillar obtained is 78 nm. This observation made it clear that the masking effect of HSQ vanishes in a range of 30 to 60 seconds. And then, pillar etching is started again, so at 60 seconds, the height of the nano pillar is reduced. We successfully implemented the nanopillar of 170 nm with AMAT recipe.  In Future Scope since for GAA TFET, the pillar height required for fabrication is 250-300 nm. So, some more optimization with resist spinning and etching chemistry will be required to do further. The proposed HSQ optimization method for implementation of Nanopillar found innovative and simple due to better convenience of pattern transfer and selectivity from resist to various materials.

ACKNOWLEDGEMENT
This work was supported by INUP (Indian Nano electronics User Program) and was carried out at Centre of Excellence (CEN’s) lab at IIT Bombay. Government of India and MCIT sponsored this project under INUP. Author would like to thanks Dr. K. Nageshwari for her consistent support. 

CONFLICT OF INTEREST
The authors declare that there is no conflict of interests regarding the publication of this manuscript.

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