Predictive physics based simulation of nano scale gate-all-around field effect transistor under the influence of high-k gate dielectrics

Document Type : Research Paper


1 Department of Electronics, Technical and Vocational University, Kashan, Iran.

2 Institute of nanoscience and nanotechnology, University of Kashan, Iran.


In this paper the electrical characteristics of a nano scale silicon gate-all-around field effect transistor (GAA-FET) with different dielectrics in the gate electrode are predicted. For this, we first calibrate physics based TCAD simulator against experimental results reported by IBM. Then the device electrical figures of merit comprised of ION/IOFF, transconductance (gm) and subthreshold slope (SS) are extracted. The obtained results show that utilizing various high-k gate dielectrics has a noticeable impact on the device performance. Different high-k gate dielectrics comprised of Al2O3, Si3N4 and HfO2 are explored in our study. Moreover, when high-k gate dielectric is used instead of conventional SiO2 insulator, the electrical characteristics will be improved in terms of ION/IOFF ratio, transconductance to drive current ratio (gm/IDS) and SS. Based on our simulations and obtained results, scaling GAA-FETs by utilizing high-k dielectrics offers superior electronic devices and promising candidates for “more Moore” domain and integrated circuit applications.



To increase electrical performance in integrated circuit (IC), shrinking the size of transistors is aggressively performed. Although continuous scaling in semiconductor transistors can increase device density and performance, but appearance of short channel effects (SCE) and degradation of electrical characteristics of CMOS transistors in subthreshold region are unwanted results of scaling[1-7]. As gate oxide thickness reaches below one nanometer for enhancing device electrical performance aim, the problem of gate leakage current due to quantum tunneling along SiO2 increases[2, 4].Therefore it is necessary to replace conventional SiO2 insulator by a material with higher dielectric constant to increase gate oxide thickness while having excellent electrical performance. Recently, device designers have offered variety of materials, geometries and technologies to overcome aforementioned problems. Utilizing of 2-D materials [8-12], high-k dielectrics and device geometries comprising of tunnel FET (TFET)[13-21], FINFET and GAA-FET [22-28], are some of these suggestions.

In GAA-FET due to the fact that the gate electrode has surrounded the entire channel volume, gate electrostatic control over the channel region is higher compared to single gate, double gate, tri-gate and omega/pi-gate structures, electrical characteristics can be further improved[29, 30]. Thus, it is predicted that GAA-FET can be a promising candidate with maximum capability to expand Moor’s law[31]. However the main concern of GAA-FET is high OFF-current and subthreshold slope caused by scaling which limits the device performance for low power and steep switching applications[32]. Precise prediction and improvement in the electrical performance of ultra-short channel GAA-FETs necessitates taking quantum theory into account. This is due to the fact that quantum confinement and electron wave behavior is dominant in these devices[33].

In this work, we have considered a circular cross section GAA-FET and predicted its electrical characteristics by utilizing four different dielectrics i.e. HfO2, Al2O3, Si3N4 and SiO2. For this we have calibrated the simulator with experimental results using quantum models and solving Schrödinger equations in transverse direction where confinement occurs. Since Si-SiO2 interface has better quality in fabrication process [2, 34], gate dielectric for all four devices under study is comprising of two layers of SiO2 on silicon channel and a high-k dielectric on top of SiO2.

The rest of this paper consists of three other sections. In section II we explain the device geometry and its parameters along with simulation considerations. Electrical characteristic results are discussed in section III. A comprehensive conclusion about this work is offered in section IV.


Fig. 1 depicts a schematic view of GAA-FET device understudy. The cross section of this structure is circular. The silicon semiconductor channel has been covered by 0.5 nm silicon oxide and these two layers have been surrounded by 1nm high-k dielectric. This is due to better matching and interface quality of Si-SiO2which is formed in the fabrication process. All parameters of the physical and dimensional parameters related to this work are presented in Table 1.

Silvaco ATLAS simulator can predict the electrical characteristics of semiconductor devices at different bias conditions [35]. To have reliable results we first calibrated the simulator against experimental results from IBM as presented in [36], [37] and [23]. For this we estimated the 40.21 nm perimeter of silicon channel reported in [37] by a circle with radius of 6.4 nm and then fitted its electrical characteristics by setting conduction band effective mass and mobility for electrons. Fig.2(a,b) depict transfer characteristics (ID-VGS) and Gaussian like doping profile incorporated in the device for calibration at two low and high bias points corresponding to VDS=0.05 V and VDS=1.0 V, respectively.

In this work we enabled Schrodinger model to predict quantized density of states in the transverse direction (radius) for different orbital quantum numbers, where quantum mechanical confining potential variations occur. Solving self-consistent Schrödinger’s and Poisson’s equations can iteratively calculate carrier concentration (using eigen energies and wave functions) along with potential profiles and then the current in the device at each bias. Once carrier concentration is calculated, it is substituted in charge part of Poisson’s equation. Then the potential extracted from Poisson’s equation is substituted back into Schrödinger’s equation. Alternating between Schrödinger’s and Poisson’s equations continues until a self-consistent convergence is obtained. We also enabled drift-diffusion mode-space (dd-ms) model. This is a semi-classical model to transport in devices with confinement in transverse direction and it has performed as an alternative to fully quantum non-equilibrium green’s function (NEGF) model. However, the classical drift-diffusion equation is solved instead of quantum transport equation in this model. So, quantum effects in transverse direction is performed (by Schrödinger model), while all models related to mobility and recombination can be inherited. It is worth noting that calculation and simulation time in dd-ms model is faster than NEGF [31].

It should be noted that the aim of this work is prediction and evaluation of the electrical characteristics of the calibrated GAA-FET with different high-k materials in terms of ON-current, OFF-current, subthreshold slope and transconductance.


The transfer characteristics (ID-VGS) of the device under study with four different dielectrics has been shown in Fig. 3 at VDS=0.05 V and VDS=1.0V. According to this figure as the permittivity of gate dielectric increases drain current enhances and both OFF-current along with subthreshold slope (SS) are decreased. Therefore, GAA-FET with HfO2gate dielectric seems much interesting for digital applications. This improvement in the device with higher permittivity dielectric is due to better electrostatic controllability of the gate over surrounded channel which intensively controls all of the carriers tending to pass from source to drain through the channel. Fig. 4 (a) depicts contour plot of electron concentration in the device at VDS=VGS=1.0 V for GAA-FET with HfO2. Quantum confinement effect and receding electrons from Si-SiO2 interface is obvious in this figure (a,b). First- three electron wave functions are presented in Fig. 4(c).Since squared wave function represent the electron occupation probability[33], electron concentration is expected to be lower in Si-SiO2 interface. This is in agreement with achieved results of physical TCAD simulation as illustrated in Fig. 4(c). In fact, due to formation of a quantum well in Si-SiO2 interface, electron energy will be quantized in transverse direction and electron wave-like behavior will be dominant which results in a reduction of electron concentration at the interface.

Transconductance (gm), shows how much the gate voltage influences on the drain current and is defined by following relation:


This is an important parameter and shows amplification rate, somehow. Another parameter, gm/ID, reveals how much of energy dissipation (ID), has led to amplification (gm) in a device [2]. Based on this and Fig. 5 it is obvious that as the gate dielectric constant increases, gm/ID ratio will be enhanced and this improvement is higher at lower gate voltages (VGS). According to this figure, GAA-FET with HfO2 dielectric has higher gm/ID ratio compared to other counterparts and it is because of better subthreshold region behavior in this device.

In another investigation, the channel length of GAA-FET with different high-k materials has been scaled down and then ION/IOFF ratio along with SS for channel lengths of 32nm, 22nm and 14 nm were investigated. According to Fig. 6 by scaling, ION/IOFF ratio is decreased while SS is increased for all device GAA-FET with different dielectrics, and the degradation amount for the device with lower permittivity is more. This is due to this reality that by scaling, the gate influence on the device performance particularly in subthreshold region reduces, which this can be partly compensated by using high-k dielectrics.


In this work we investigated the electrical characteristics of a GAA-FET with different high-k dielectric materials in the gate comprising of HfO2, Al2O3, Si3N4 and SiO2. It was shown that GAA-FET with HfO2dielectric has better performance in terms of ION, IOFF, SS and gm/ID ratio. Our physical simulations also showed that both ION/IOFF and SS parameters were degraded by scaling, and this is mostly related to subthreshold slope behavior degradation, where off-state current increases in the device. Based on our predictive simulation results, using high-k dielectric in the gate can improve the device electrical characteristics and it is seriously necessary for following Moore’s low.


The authors declare that there is no conflict of interests regarding the publication of this manuscript.


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